FPGA Architecture
Logic Explorer

1. FPGA Introduction

(i)   A Field-Programmable Gate Array is a semiconductor device containing progammable logic components called "logic blocks", and programmable interconnects.

(ii)   Logic blocks can be programmed to perform the function of basic logic gates such as AND,NAND,OR,XOR or more complex combinational functions such as decoders or mathematical functions. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.

(iii)   FPGAs can be reprogrammed to desired application or functionality requirements after manufacturing. This feature distinguishes FPGAs from Application Specific Integrated Circuits (ASICs), which are custom manufactured for specific design tasks. Although one-time programmable FPGAs are available, the dominant types are SRAM based which can be programmed as the design evolves.

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(iv)   Simulations and prototyping are really vital part of the electronics industry since a very long time now. Before heading sure the particular fabrication of hardware, everybody would wish to take care that whatever they are creating will work that means they require it to. Over all these years while electronics companies offered dedicated hardware in their products, it was not possible for the end user to reconfigure them to his own needs.

(v)   This need led to the growth of a new market segment of customer configurable Field Programmable integrated circuits called "Field Programmable Gate Arrays or FPGAs".

(vi)   FPGAs(Field Programmable Gate Arrays) are amazing devices that now allow the average person to create their very own digital circuits. The cost has come down enough that you don't have to be a huge company to get your hands dirty.

(vii)   You can think of an FPGA as a blank slate. By itself an FPGA does nothing. It is up to the designer to create a configuration file, often called a bit file, for the FPGA. Once loaded the FPGA will behave like the digital circuit you designed.

2.  FPGA Application

Due to their programmable nature, FPGAs are an ideal fit for many different markets. As the industry leader, Xilinx provides comprehensive solutions consisting of FPGA devices, advanced software, and configurable, ready-to-use IP cores for markets and applications such as:

(i)   Aerospace & Defense
(ii)  ASIC Prototyping
(iii)  Wireless Communications
(iv)  Wired Communications
(v)  Video & Image Processing
(vi)  Security
(vii)  Medical
(viii)  Industrial
(ix)  Broadcast

3.  FPGA Configuration

1.  Xilinx® 7 series FPGAs are configured by loading application-specific configuration data-a bitstream-into internal memory.

2.In any case, there are two general configuration datapaths;

(a) The first is the serial datapath that is used to minimize the device pin requirements.

    (b) The second datapath is the 8-bit, 16-bit, or 32-bit datapath used for higher performance or access (or link) to industry-standard interfaces, ideal for external data sources like processors, or x8- or x16-parallel flash memory.

3.Like processors and processor peripherals, Xilinx FPGAs can be reprogrammed, in system, on demand, an unlimited number of times.

4.Because Xilinx FPGA configuration data is stored in CMOS configuration latches (CCLs), it must be reconfigured after it is powered down. The bitstream is loaded each time into the device through special configuration pins.

These configuration pins serve as the interface for a number of different configuration modes:

(i) Master-Serial configuration mode.

(ii) Slave-Serial configuration mode.

(iii) Master Select MAP(parallel) configuration mode (x8 and x16).

(iv) Slave Select MAP (parallel) configuration mode (x8, x16, and x32)

(v) JTAG/boundary-scan configuration mode.

(vi) Master Serial Peripheral Interface (SPI) flash configuration mode (x1, x2,       x4).

(vii) Master Byte Peripheral Interface (BPI) flash configuration mode (x8 and       x16) using parallel NOR flash.

5. Dedicated mode input - M[2:0]. The M2, M1, M0 mode pins should be set at     a constant DC Voltage level, either through pull-up or pull-down resistor(<=     1K) or tied to ground. The mode pins should not be toggled during and after    configuration.

6. The terms Master and Slave refer to the direction of the configuration clock (CCLK):

(a) In Master configuration modes, the 7 series device drives CCLK from an internal oscillator.

(b) In Slave configuration modes, CCLK is an input.

7. The JTAG/boundary-scan configuration interface is always available,     regardless of the mode pin settings.


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